Method of fabricating printed circuit board having thin core layer

ABSTRACT

A method is directed towards fabricating a printed circuit board (PCB) having a thin core layer. In the method, a substrate, where a copper foil is formed on a release film and a prepreg, is employed as a base substrate and a core insulating layer is removed after the fabrication of the PCB, thereby reducing the thickness of the final product.

INCORPORATION BY REFERENCE

The present application claims priority under 35 U.S.C. §119 to KoreanPatent Application No. 10-2004-0100585 filed on Dec. 2, 2004. Thecontent of the application is incorporated herein by reference in itsentirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a printedcircuit board (PCB). More particularly, the present invention pertainsto a method of fabricating a PCB, in which a substrate, where a copperfoil is formed on a release film and a prepreg, is employed as a basesubstrate and a core insulating layer is removed after the fabricationof the PCB, thereby reducing the thickness of the final product.

2. Description of the Prior Art

In accordance with the trend of miniaturization and slimming ofelectronic goods, a size of a package tends to be reduced. In thisregard, the total size of the package depends on the size of a substrateused in the package.

FIGS. 1 a to 1 m are sectional views illustrating the stepwisefabrication of a six-layered PCB in the conventional build-up manner. Inthe specification of the present invention, the term “build-up manner”means a process which comprises forming internal layers and layeringexternal layers one by one on the internal layers.

FIG. 1 a is a sectional view of an unprocessed copper clad laminate(CCL) 101. Copper foils 102 are applied onto an insulating layer 103.Generally, the copper clad laminate acts as a substrate of a PCB, andmeans a thin laminate consisting of the insulating layer onto whichcopper is thinly applied.

The copper clad laminate is classified into a glass/epoxy CCL, aheat-resistant resin CCL, a paper/phenol CCL, a high-frequency CCL, aflexible CCL (polyimide film), a complex CCL, and the like, inaccordance with its use. Of them, the glass/epoxy CCL is most frequentlyused to fabricate double-sided PCBs and multilayer PCBs.

The glass/epoxy CCL consists of a reinforcing base substance in which anepoxy resin (combination of a resin and a curing agent) is penetratedinto a glass fiber, and a copper foil. The glass/epoxy CCL is gradedFR-1 to FR-5, as prescribed by the National Electrical ManufacturersAssociation (NEMA), in accordance with the kind of reinforcing basesubstance and heat resistance. Traditionally, the FR-4 grade ofglass/epoxy CCL is most frequently used, but recently, the demand forthe FR-5 grade of glass/epoxy CCL, which has improved glass transitiontemperature (T_(g)), is growing.

In FIG. 1 b, the copper clad laminate 101 is drilled to form a via hole104 for interlayer connection.

In FIG. 1 c, electroless copper plating and electrolytic copper platingprocesses are conducted. In this regard, the electroless copper platingprocess is conducted before the electrolytic copper plating process. Thereason that the electroless copper plating process is conducted beforethe electrolytic copper plating process is that the electrolytic copperplating process using electricity is not possible on the insulatinglayer. In other words, the electroless copper plating process isconducted as a pretreatment process to form a thin conductive filmneeded to conduct the electrolytic copper plating process. Since it isdifficult to conduct the electroless copper plating process and toassure economic efficiency, it is preferable that a conductive part of acircuit pattern be formed using the electrolytic copper plating process.

Subsequently, a paste 106 is packed in the via hole 104 so as to protectelectroless and electrolytic copper plating layers 105 formed on a wallof the via hole 104. The paste is generally made of an insulating inkmaterial, but may be made of a conductive paste according to theintended use of the PCB. The conductive paste includes a mixture of anyone metal, which is selected from Cu, Ag, Au, Sn, Pb, or an alloythereof and acts as a main component, and an organic adhesive. However,the process of plugging the via hole 104 using the paste may be omittedaccording to the purpose of the MLB.

In FIG. 1 c, for convenience of understanding, the electroless andelectrolytic copper plating layers 105 are illustrated as one layerwithout distinguishing two layers from each other.

In FIG. 1 d, an etching resist pattern 107 is constructed to form acircuit pattern for an internal circuit.

A circuit pattern, which is printed on an artwork film, must betranscribed on the substrate so as to form the resist pattern. Thetranscription may be conducted through various methods, but the mostfrequently used method is to transcribe a circuit pattern, which isprinted on an artwork film, onto a photosensitive dry film usingultraviolet rays. Recently, a liquid photo resist (LPR) has sometimesbeen used instead of the dry film.

The dry film or LPR to which the circuit pattern is transferred acts asthe etching resist 107, and when the substrate is dipped in an etchingliquid as shown in FIG. 1 e, the circuit pattern is formed.

After the formation of the circuit pattern, the appearance of thecircuit pattern is observed using an automatic optical inspection (AOI)device so as to evaluate whether an internal circuit is correctly formedor not, and the resulting substrate is subjected to a surface treatment,such as a black oxide treatment.

The AOI device is used to automatically inspect the appearance of a PCB.The device automatically inspects the appearance of the PCB employing animage sensor and a pattern recognition technology using a computer.After reading information regarding the pattern of an objective circuitusing the image sensor, the AOI device compares the information toreference data to evaluate whether defects have occurred or not.

The minimum value of an annular ring of a land (a portion of the PCB onwhich parts are to be mounted) and a ground state of a power source canbe inspected by use of the AOI device. Furthermore, the width of thecircuit pattern can be measured and the omission of a hole can bedetected. However, it is impossible to inspect the internal state of ahole.

The black oxide treatment is conducted so as to improve adhesionstrength and heat resistance before an internal layer having the circuitpattern is attached to an external layer.

In FIG. 1 f, resin-coated copper (RCC) is applied to both sides of theresulting substrate. The RCC consists of a substrate in which a copperfoil 109 is formed on only one side of a resin layer 108, and the resinlayer 108 acts as an insulator between the circuit layers.

In FIG. 1 g, a blind via hole 110 is formed to electrically connect theinternal and external layers to each other. The blind via hole may bemechanically drilled. However, it is necessary to more precisely conductthe drilling in comparison with processing of a through hole, and thus,it is preferable to use an yttrium aluminum garnet (YAG) laser or a CO₂laser. The YAG laser can drill both a copper foil and an insulatinglayer, but the CO₂ laser can drill only the insulating layer.

In FIG. 1 h, an external layer 111 is laminated according to a platingprocess.

In FIG. 1 i, the external layer 111 formed as shown in FIG. 1 h ispatterned according to the same procedure as the formation of thecircuit pattern of the internal layer. The patterned external layer 111is then inspected in terms of the circuit and subjected to a surfacetreatment, as in the case of the circuit pattern of the internal layer.

In FIG. 1 j, additional RCC is applied to both sides of the resultingsubstrate. This RCC includes a resin layer 112 and a copper foil 113coated on one side of the resin layer 112, and the resin layer 112 actsas an insulator.

In FIG. 1 k, a blind via hole 114 is formed to electrically connect theexternal layers to each other using the laser as described above.

In FIG. 1 l, the additional external layer 115 is laminated according toa plating process.

In FIG. 1 m, the additional external layer 115 is patterned according tothe same procedure as the external layer 111, and the circuits of thepatterned external layer 115 are then inspected and the layer issubjected to a surface treatment.

The number of layers constituting the multilayer PCB may be continuouslyincreased by repeating the lamination of layers, the construction of thecircuit patterns, the inspection of the circuit patterns, and thesurface treatment of the resulting structure.

Subsequently, a photo-solder resist and an Ni/Au layer are formed on theresulting circuit pattern, thereby creating a six-layered PCB.

In a conventional method of fabricating a substrate (PCB), an organicresin is used as an insulating layer to form a copper clad laminate(CCL) which is plated with Cu on both sides thereof. In this regard, theorganic resin also acts as a backbone to support a product so as to keepits shape. Hence, it is necessary that a thickness of the product be 50μm or more so as to keep the shape. In other words, when the thicknessis the above limit or less, it is impossible to fabricate the productusing a typical organic resin.

With respect to this, U.S. Pat. No. 6,696,764 discloses a method offabricating two PCBs by cutting a central part of the PCB through amechanical process after construction of the PCB. However, since thecutting is mechanically conducted, it has limited application to thefabrication of a precise PCB. Additionally, a core insulating layerremains after the cutting, making the PCB thick.

Accordingly, a more fundamental alternative proposal is needed to reducea thickness of the PCB.

SUMMARY OF THE INVENTION

Therefore, the present invention has been made keeping in mind the abovedisadvantages occurring in the prior arts, and an object of the presentinvention is to provide a method of fabricating a slim PCB, in which acore insulating layer conventionally used is removed from a finalproduct, thereby reducing the total thickness of the PCB.

The above object can be accomplished by providing a method offabricating a PCB, which comprises preparing a base substrate whichcomprises a core insulating layer, release films attached to the coreinsulating layer, insulators laminated so as to surround the releasefilms, and copper foils laminated on upper and lower sides of aresulting structure; forming solder resists on upper and lower sides ofthe base substrate; sequentially laminating circuit layers andinsulating layers on upper and lower sides of the resulting basesubstrate; cutting edge portions of the resulting substrate so as toremove the edge portions which contain the insulators surrounding therelease films; detaching the release films to divide the resultingsubstrate into two substrates so that the two substrates are separatedfrom the core insulating layer; and removing the exposed copper foilsfrom sides of the separated substrates.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and other advantages of thepresent invention will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings, in which:

FIGS. 1 a to 1 m are sectional views stepwisely illustrating thefabrication of a six-layered PCB in the conventional build-up manner;and

FIGS. 2 a to 2 n are sectional views stepwisely illustrating thefabrication of a PCB according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 2 a to 2 n are sectional views stepwisely illustrating thefabrication of a PCB according to the present invention.

First, a base substrate 200 is formed as shown in FIG. 2 a.

Release films 202 adhere to upper and lower sides of a core insulatinglayer 201, and insulators 203 are laminated so as to surround therelease films 202. Subsequently, copper foils 204 a, 204 b are laminatedto cover the release films 202 and the insulators 203. Proper pressureand heat are applied to upper and lower sides of the resulting substrateto press the resulting substrate.

An epoxy resin, which is incorporated in a glass fiber constituting thecentral layer of a conventional CCL, may be used as the core insulatinglayer 201. A prepreg, which is frequently used as an interlayerinsulating material in the course of fabricating a conventional PCB, maybe employed as the insulators 203.

The release films 202 are laminated on the core insulating layer 201,and the insulators 203 surround the release films. The copper foils 204a, 204 b are laminated on the release films 202 and the insulators 203.A thickness of each of the copper foils 204 a, 204 b is about 10 μm.

The insulators 203 serve to physically support the copper foils 204 a,204 b, thereby preventing the copper foils 204 a, 204 b from crumplingor tearing in the course of fabricating the PCB.

In FIG. 2 b, a photosensitive solder resist 205 is applied, exposed anddeveloped using a mask film, on which a predetermined circuit pattern isprinted, to be patterned. During the exposure, a portion of the solderresist, which does not receive light because light is blocked by themask film, is not transformed. However, the other portion of the solderresist, which receives light, is cured by light. Only the untransformedportion of the solder resist is removed to form the pattern. A photosolder resist may be used as the solder resist 205.

In FIG. 2 c, an electroless copper plating process is conducted to forman electroless plating layer 206 which acts as a seed layer in anelectrolytic copper plating process. It is possible to implement asputtering process instead of the electroless plating process.

In FIG. 2 d, a photosensitive plating resist 207 is applied, exposed anddeveloped to be patterned using a predetermined mask pattern.

In FIG. 2 e, after a circuit pattern 208 is formed by the electrolyticplating process, the plating resist 207 is stripped. The electrolessplating layer 206 acts as a path through which a current flows duringthe electrolytic plating process. A thickness of the circuit pattern208, which is formed through the electrolytic plating process, is about7-15 μm. After the plating resist 207 is stripped, the electrolessplating layer 206 having a thickness of about 0.3-0.5 μm, and thecircuit pattern 208, which is formed through the electrolytic platingprocess and has a thickness of about 7-15 μm, remain.

In FIG. 2 f, an exposed portion of the electroless plating layer 206 isremoved through a flash etching process.

In FIG. 2 g, an insulating layer 209 is laminated. An ink-type orsheet-type insulator may be used as the insulating layer 209. When usingthe ink-type insulator, an application process in a wet state, a curingprocess, and a brushing process are required. With respect to thesheet-type insulator, lamination and curing processes are enough.Accordingly, the sheet-type insulator is preferable in terms ofworkability and reliability. A prepreg may be used as the sheet-typeinsulator.

In FIG. 2 h, the insulating layer 209 is drilled by a laser to form avia hole 210 therethrough so as to electrically connect upper and lowerlayers to each other. Next, an electroless plating process isimplemented to form an electroless plating layer 211 for a seed layer ona wall of the via hole 210 and on a surface of the substrate.

In FIG. 2 i, a plating resist is applied, exposed and developed to bepatterned, and a circuit pattern 212 is formed through an electrolyticplating process. Subsequently, the plating resist is stripped, and aportion of the electroless plating layer 211, on which the circuitpattern 212 is not formed, is removed through a flash etching process.

In FIG. 2 j, a solder resist 213, for example, a photo solder resist, isapplied to the entire surface of the PCB.

In FIG. 2 k, a portion of the solder resist 213, at which a connectionpad of an external circuit is to be formed, is removed through exposureand development processes, and a plating process is conducted using Niand Au to form an electrode pad 214 for electric connection to theexternal circuit.

In FIG. 2 l, external portions of the PCB are cut to remove externalportions of the core insulating layer which contain the insulators 203.

Next, as shown in FIG. 2 m, the resulting double-sided PCB, whichcontains structures laminated on the release films 202, is divided intotwo PCBs 215 a, 215 b. An adsorption plate or a suction plate having asuction force is applied to both sides of the double-sided PCB and thenpulled, thereby achieving the division. Since the release films areeasily separated from the core insulating layer 201 and the copper foillayers 204 a, 204 b, it is possible to achieve the separation using lowpressure while the PCB is not damaged. Accordingly, it is unnecessary toconduct cuffing for the separation.

A copper foil 204 a, 204 b remains on one side of each of the separatedPCBs.

In FIG. 2 n, the copper foil 204 a, 204 b is removed through an etchingprocess, thereby creating the two PCBs which do not include the coreinsulating layer of a conventional CCL. The core insulating layer 201 isused to maintain physical strength in the course of fabricating the PCB,but is removed from the final product.

In a conventional PCB, a core insulating layer having a thickness of atleast 60 μm or so is included in a final product. However, as shown inFIG. 2 m, the insulating layer 209, such as a prepreg, is formed at thecenter of the PCB according to the present invention, and 30 μm or so isenough for a thickness of the insulating layer 209.

As described above, a method of fabricating a slim PCB according to thepresent invention is advantageous in that a core insulating layerconventionally used is removed from a final product, thereby reducingthe total thickness of the PCB.

The present invention has been described in an illustrative manner, andit is to be understood that the terminology used is intended to be inthe nature of description rather than of limitation. Many modificationsand variations of the present invention are possible in light of theabove teachings. Therefore, it is to be understood that within the scopeof the appended claims, the invention may be practiced otherwise than asspecifically described.

1. A method of fabricating a printed circuit board, comprising the stepsof: preparing a base substrate which comprises a core insulating layer,release films attached to the core insulating layer, insulatorsseparately formed from the core insulating layer and laminated so as tosurround the release film, to form a resulting structure; and copperfoils laminated on upper and lower sides of the resulting structure;maintaining the core insulating layer planar with the release film andthe insulators; forming the insulators to have the same thickness withthat of the release film; forming solder resists on upper and lowersides of the base substrate to form a resulting base substrate;laminating circuit layers and insulating layers sequentially on upperand lower sides of the resulting base substrate to form a resultingsubstrate; cutting edge portions of the resulting substrate so as toremove the edge portions which contain the insulators surrounding therelease films; detaching the release films to divide the resultingsubstrate into two substrates so the two substrates are separated fromthe core insulating layer; and removing the copper foils from thesubstrates.
 2. The method as set forth in claim 1, wherein the step oflaminating circuit layers and insulating layers sequentially comprisesthe steps of: laminating the insulating layers for interlayer insulationon the upper and lower sides of the resulting base substrate; formingvia holes and circuit patterns on the insulating layers; applyinginsulating solder resists; and forming electrode pads.
 3. The method asset forth in claim 1, wherein the step of preparing the base substratecomprises the steps of: attaching the release films to upper and lowersides of the core insulating layer; laminating the insulators so as tosurround the release films; laminating the copper foils on upper andlower sides of the release films and the insulators; and pressing thebase substrate.